From d15276557c65de2a1941632ec9024dea261cce26 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Benedikt=20B=C3=B6hm?= <bb@xnull.de>
Date: Tue, 7 Jul 2009 09:46:27 +0200
Subject: make instruction 64-bit wide to support more than 32 registers

---
 src/emu/cpu.c | 53 +++++++++++++++++++++++++++--------------------------
 1 file changed, 27 insertions(+), 26 deletions(-)

(limited to 'src/emu/cpu.c')

diff --git a/src/emu/cpu.c b/src/emu/cpu.c
index f083283..522e2f2 100644
--- a/src/emu/cpu.c
+++ b/src/emu/cpu.c
@@ -4,6 +4,7 @@
 #include <stdbool.h>
 #include <signal.h>
 #include <string.h>
+#include <inttypes.h>
 
 #include "cpu.h"
 #include "log.h"
@@ -11,7 +12,7 @@
 #include "opc.h"
 #include "syscall.h"
 
-/* stack pointer register*/
+/* stack pointer register */
 uint32_t SP;
 
 /* base pointer register */
@@ -31,19 +32,19 @@ uint32_t *GPR;
 
 /* extract operands from the instruction register */
 static inline
-uint32_t __OPEXT(uint32_t IR, uint8_t start, uint8_t length)
+uint64_t __OPEXT(inst_t IR, uint8_t start, uint8_t length)
 {
-        return (IR >> start) & ((1 << length) - 1);
+	return (IR >> start) & ((1ULL << length) - 1);
 }
 
 #define OPEXT(start, length) __OPEXT(IR, start, length)
 
 /* operands */
-#define OPCODE OPEXT(26, 6)
-#define REGa   OPEXT(21, 5)
-#define REGb   OPEXT(16, 5)
-#define REGc   OPEXT(11, 5)
-#define IMMc   OPEXT(0, 16)
+#define OPCODE OPEXT(58, 6)
+#define REGa   OPEXT(45, 13)
+#define REGb   OPEXT(32, 13)
+#define REGc   OPEXT(19, 13)
+#define IMMc   OPEXT(0, 32)
 
 /* cpu traps */
 void trap(int num)
@@ -67,11 +68,11 @@ void trap(int num)
 	}
 }
 
-void execute(uint32_t IR)
+void execute(inst_t IR)
 {
 	/* decode op-code */
 	uint8_t opcode = OPCODE;
-	int32_t a, b, c;
+	int64_t a, b, c;
 
 	if (opcode < OPC_MOV) {
 		/* arithmetic, logic, comparison */
@@ -79,7 +80,7 @@ void execute(uint32_t IR)
 		b = REGb;
 		c = REGc;
 
-		debug("IP@%#08x: %-4s r%i, r%i, r%i", IP,
+		debug("IP@%#08x: %-4s r%"PRIi64", r%"PRIi64", r%"PRIi64, IP,
 				opc2mnemonic(IR), a, b, c);
 	}
 
@@ -90,17 +91,17 @@ void execute(uint32_t IR)
 		c = IMMc;
 
 		/* sign extension */
-		if (c >= 0x8000)
-			c -= 0x10000;
+		if (c >= 0x80000000)
+			c -= 0x100000000;
 
 		if (opcode < OPC_LW) {
-			debug("IP@%#08x: %-4s r%i, %i", IP,
+			debug("IP@%#08x: %-4s r%"PRIi64", %"PRIi64, IP,
 					opc2mnemonic(IR), a, c);
 		} else if (opcode < OPC_PUSH) {
-			debug("IP@%#08x: %-4s r%i, r%i, %i", IP,
+			debug("IP@%#08x: %-4s r%"PRIi64", r%"PRIi64", %"PRIi64, IP,
 					opc2mnemonic(IR), a, b, c);
 		} else {
-			debug("IP@%#08x: %-4s r%i", IP,
+			debug("IP@%#08x: %-4s r%"PRIi64, IP,
 					opc2mnemonic(IR), a);
 		}
 	}
@@ -112,20 +113,20 @@ void execute(uint32_t IR)
 		c = IMMc;
 
 		/* sign extension */
-		if (c >= 0x8000)
-			c -= 0x10000;
+		if (c >= 0x80000000)
+			c -= 0x100000000;
 
 		switch (opcode) {
 		case OPC_BEZ:
-			debug("IP@%#08x: %-4s r%i, %i", IP,
+			debug("IP@%#08x: %-4s r%"PRIi64", %"PRIi64, IP,
 					opc2mnemonic(IR), a, c);
 			break;
 		case OPC_JMP:
-			debug("IP@%#08x: %-4s %i", IP,
+			debug("IP@%#08x: %-4s %"PRIi64, IP,
 					opc2mnemonic(IR), c);
 			break;
 		case OPC_CALL:
-			debug("IP@%#08x: %-4s %i", IP,
+			debug("IP@%#08x: %-4s %"PRIi64, IP,
 					opc2mnemonic(IR), c);
 			break;
 		case OPC_RET:
@@ -215,16 +216,16 @@ void execute(uint32_t IR)
 		break;
 	case OPC_BEZ:
 		if (GPR[a] == 0) {
-			IP += c * 4;
+			IP += c * sizeof(inst_t);
 			return;
 		}
 		break;
 	case OPC_JMP:
-		IP += c * 4;
+		IP += c * sizeof(inst_t);
 		return;
 	case OPC_CALL:
-		push(IP + 4);
-		IP += c * 4;
+		push(IP + sizeof(inst_t));
+		IP += c * sizeof(inst_t);
 		return;
 	case OPC_RET:
 		IP = pop();
@@ -237,5 +238,5 @@ void execute(uint32_t IR)
 		trap(TRP_ILL);
 	}
 
-	IP += 4;
+	IP += sizeof(inst_t);
 }
-- 
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